Texas Instruments /MSP432E411Y /LCD0 /RASTRTIM2

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Interpret as RASTRTIM2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LCD_RASTRTIM2_MSBHFP 0LCD_RASTRTIM2_MSBHBP 0LCD_RASTRTIM2_ACBF 0LCD_RASTRTIM2_ACBI 0 (LCD_RASTRTIM2_IVS)LCD_RASTRTIM2_IVS 0 (LCD_RASTRTIM2_IHS)LCD_RASTRTIM2_IHS 0 (LCD_RASTRTIM2_INVPXLCLK)LCD_RASTRTIM2_INVPXLCLK 0 (LCD_RASTRTIM2_INVOE)LCD_RASTRTIM2_INVOE 0 (LCD_RASTRTIM2_PSYNCRF)LCD_RASTRTIM2_PSYNCRF 0 (LCD_RASTRTIM2_PXLCLKCTL)LCD_RASTRTIM2_PXLCLKCTL 0 (LCD_RASTRTIM2_MSBLPP)LCD_RASTRTIM2_MSBLPP 0LCD_RASTRTIM2_HSW

Description

LCD Raster Timing 2

Fields

LCD_RASTRTIM2_MSBHFP

Bits 9:8 of the horizontal front porch field

LCD_RASTRTIM2_MSBHBP

Bits 9:8 of the horizontal back porch field

LCD_RASTRTIM2_ACBF

AC Bias Pin Frequency

LCD_RASTRTIM2_ACBI

AC Bias Pins Transitions per Interrupt

LCD_RASTRTIM2_IVS

Invert Vsync

LCD_RASTRTIM2_IHS

Invert Hysync

LCD_RASTRTIM2_INVPXLCLK

Invert Pixel Clock

LCD_RASTRTIM2_INVOE

Invert Output Enable

LCD_RASTRTIM2_PSYNCRF

Program HSYNC/VSYNC Rise or Fall

LCD_RASTRTIM2_PXLCLKCTL

Hsync/Vsync Pixel Clock Control On/Off

LCD_RASTRTIM2_MSBLPP

MSB of Lines Per Panel

LCD_RASTRTIM2_HSW

Bits 9:6 of the horizontal sync width field

Links

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